Semiconductor integrated circuit apparatus in current technology are often fabricated by forming recesses at the major surface of a semiconductive silicon body and then filling the recesses with silicon dioxide by selective oxidation, typically using silicon nitride films as masks; thereby, recessed oxide isolation zones or regions are created for the purpose of electrically isolating different circuit portions. In the ordinary thermal oxide growth processes for filling recesses with oxide, however, undesirable structures are produced at the edge of the recess, recognized in the prior art as the "bird's beak" and "bird's head" or crest. This problem is described, for example, in "Topology of Silicon Structures with Recessed SiO.sub.2 " by E. Bassous, H. N. Yu and V. Maniscalco, J. Electrochem. Soc., Nov. 1976, Vol. 123, No. 11, pages 1729-1737, and in U.S. Pat. No. 4,002,511 to Magdo et al.
More specifically, the above-cited reference of Magdo et al purposes a technique for reducing the "bird's beak" aspect of the problem by increasing the extent of the silicon nitride mask so that it contacts and covers a portion of the exposed silicon. However, because of the isotropic growth of the oxide from all surfaces of the recess, a protuberance or "bird's head" still forms in the peripheral surface of the recessed oxide isolation zone. Moreover, a "bird's beak" still may form to some extent, particularly where another oxide layer is present next to the silicon. Thus the integrated circuit device lacks the desired planarity; accordingly, the subsequent formation of overlayers of dielectric and conductive materials is rendered difficult and generally unsatisfactory.
In U.S. Pat. No. 3,958,040, issued to Webb on May 18, 1976, a technique for reducing the "bird-head" problem is disclosed in which the growth of silicon dioxide from the sidewalls of the recesses is inhibited by a masking layer of silicon nitride on these sidewalls, in order to enable the fabrication of a more smooth topology on the top surface of the resulting recess oxide. However, such a technique does not in practice result in a sufficiently smooth topology for satisfactory further device processing.
Accordingly, it would be desirable to have a method of fabricating semiconductor integrated circuits having recessed oxide isolation zones which are substantially planar and are free of any substantial surface proturberances.